Skip to content
Snippets Groups Projects
Commit 7d6b8ea0 authored by Pascal GOUEDO's avatar Pascal GOUEDO
Browse files

CV32E40Pv2 index.html updates. 


Signed-off-by: default avatarPascal Gouedo <pascal.gouedo@dolphin.fr>
parent f17db727
No related branches found
No related tags found
1 merge request!686CV32E40Pv2 index.html updates.
Hide whitespace changes
Inline Side-by-side
Project-Descriptions-and-Plans/CV32E40Pv2/Milestone-data/RTL_v1.8.3/index.html
+ 17
− 25
View file @ 7d6b8ea0
......@@ -18,8 +18,6 @@
If that does not answer you question(s), please do raise an issue.</p>
</head>
<br>
<!-- <body style="background-color:powderblue;"> -->
<h2>CV32E40P v1.8.3 database</h2>
<p>Database for the cv32e40p_v1.8.3 release.</p>
......@@ -31,7 +29,18 @@
<li>Siemens Questa Processor: 2024.2</li>
</ul>
<br>
<h2>CV32E40P RTL Configurations</h2>
<ul>
<p> XPULP instruction are xcvhwlp_xcvmem_xcvmac_xcvbi_xcvalu_xcvsimd_xcvbitmanip </p>
<li>CFG_P : supports RV32IMCZicsr_Zifencei_XPULP </li>
<li>CFG_P_F0: supports RV32IMFCZicsr_Zifencei_XPULP </li>
<li>CFG_P_F1: supports RV32IMFCZicsr_Zifencei_XPULP </li>
<li>CFG_P_F2: supports RV32IMFCZicsr_Zifencei_XPULP </li>
<li>CFG_P_Z0: supports RV32IMC_Zfinx_Zicsr_Zifencei_XPULP </li>
<li>CFG_P_Z1: supports RV32IMC_Zfinx_Zicsr_Zifencei_XPULP </li>
<li>CFG_P_Z2: supports RV32IMC_Zfinx_Zicsr_Zifencei_XPULP </li>
<p>Configurations with COREV_CLUSTER = 1 are not verified.</p>
</ul>
<h2>CV32E40P v1.8.3 RISCOF Reports</h2>
<ul>
......@@ -41,11 +50,10 @@
<li>CFG_P_F2: <a href="Reports/RISCOF/CFG_P_F2/report.html">CFG_P_F2 RISC Report</a></li>
</ul>
<br>
<h2>CV32E40P v1.8.3 Verification Plan(s) (aka Test Plans)</h2>
<p>Main verification methodology was through the use of RISC-V ISA Formal Verification where all RISC-V standard and custom extension (XPULP) instructions are formally verified against Sail models.<br>
A tool was then used to generate assertion for each of these instructions additionally to OBI interfaces assertions and to some pipeline assetions.</p>
Siemens Questa Processor tool was then used to generate assertion for each of these instructions additionally to OBI interfaces assertions and to some pipeline assertions.<br>
After that assertions generation step, the same tool was used to formally verify all those assertions on 2 configurations: CFG_P and CFG_P_F0.</p>
<p>Then Simulation verification was used to verify what can't be modelized and verified using Formal, like Hardware Loops, Prefetch and Fetch pipeline stages...</p>
<ul>
<li>RISC-V ISA Formal Verification Plan:<br>
......@@ -53,13 +61,12 @@
</li>
<li>Simulation Verification Plans:<br>
Overall description of simulation verification plans can be found <a href="https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/README.md">here</a>.<br>
A file listing all the tests is available <a href="https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/CV32E40Pv2_test_list.xlsx">here</a>.
ci_check are run and all v1 legacy tests are run in v2 regression as well. They were enhanced to be v1 and v2 compliant.<br>
A file listing all the tests is available <a href="https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/CV32E40Pv2_test_list.xlsx">here</a>.<br>
Full test suites are executed on the 7 configurations listed above.
</li>
<br>
</ul>
<br>
<h2>CV32E40P v1.8.3 Verification Results</h2>
<p>Results for the cv32e40p_v1.8.3 release:</p>
<ul>
......@@ -80,21 +87,6 @@
<br>
<h2>Declarations</h2>
<p>1) Full test suites and verifications are executed on 7 configurations listed below. </p>
<ul>
<p> XPULP instruction are xcvhwlp_xcvmem_xcvmac_xcvbi_xcvalu_xcvsimd_xcvbitmanip </p>
<li>CFG_P : supports RV32IMCZicsr_Zifencei + XPULP </li>
<li>CFG_P_F0: supports RV32IMFCZicsr_Zifencei + XPULP </li>
<li>CFG_P_F1: supports RV32IMFCZicsr_Zifencei + XPULP </li>
<li>CFG_P_F2: supports RV32IMFCZicsr_Zifencei + XPULP </li>
<li>CFG_P_Z0: supports RV32IMC_Zfinx_Zicsr_Zifencei_XPULP </li>
<li>CFG_P_Z1: supports RV32IMC_Zfinx_Zicsr_Zifencei_XPULP </li>
<li>CFG_P_Z2: supports RV32IMC_Zfinx_Zicsr_Zifencei_XPULP </li>
</ul>
<p>2) COREV_CLUSTER configuration is not verified. </p>
<p>3) ci_check are run and all v1 legacy tests are run also in v2 regression. They were enhanced to be v1 and v2 compliant tests.</p>
</body>
</html>
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment

Copyright © Eclipse Foundation, Inc. All Rights Reserved.     Privacy Policy | Terms of Use | Copyright Agent