:doc: update interrupts and exceptions

Created by: davideschiavone

Update doc for interrupts and exceptions.

Special attention should be taken in this sentence:

The NMI is enabled independent of the values in the mstatus and mie CSRs, and it is not visible through the mip CSR. It has interrupt ID 31, i.e., it has the highest priority of all interrupts and the core jumps to the trap-handler base address (in mtvec) plus 0x7C to handle the NMI. When handling the NMI, all interrupts including the NMI are ignored. Nested NMIs are not supported.

Is it what we want? The work has been inspired by the Ibex spec and documentation.