Fixex supported instruction set section
Created by: Silabs-ArjanB
Fixed 'supported instruction set' section according to agreed feature list of https://github.com/openhwgroup/core-v-docs/blob/master/cores/cv32e40p/CV32E40P_and%20CV32E40_Features_Parameters.pdf.
More specifically:
- Added Zifencei
- Added Zicsr
- Removed support for RV32A Standard Extension for Atomic Instructions
- Stated that Hardware Loops are optional
- Updated FPU section with info about PULP_ZFINX parameter
Signed-off-by: Arjan Bink Arjan.Bink@silabs.com