Cleaned up CSR chapter, added missing CSRs, corrected access permissions. Fixed CSR addresses.

Created by: Silabs-ArjanB

• Added missing CSRs: mvendorid, marchid, mimpid, misa, mcounteren, mscratch, mtval
• Corrected access permissions: tselect, tdata3, mcontext, scontext, mip, mip1
• Moved FPU CSRs into CSR chapter
• Put CSRs in a logical order
• Made clear which CSRs are custom
• Removed unneeded info (bit patterns)
• Fixed CSR addresses according to https://github.com/openhwgroup/cv32e40p/pull/376

The https://github.com/openhwgroup/cv32e40p/pull/376 pull request makes the following fixes:

CSR                     Old address     New address     Comment
---------------------------------------------------------------
HWLoop0_START           12'h7C0         12'h800         Needs to be User accessible (now in user custom read/write space)
HWLoop0_END             12'h7C1         12'h801         Needs to be User accessible (now in user custom read/write space)
HWLoop0_COUNTER         12'h7C2         12'h802         Needs to be User accessible (now in user custom read/write space)
HWLoop1_START           12'h7C4         12'h804         Needs to be User accessible (now in user custom read/write space)
HWLoop1_END             12'h7C5         12'h805         Needs to be User accessible (now in user custom read/write space)
HWLoop1_COUNTER         12'h7C6         12'h806         Needs to be User accessible (now in user custom read/write space)
FPREC                   12'h006         12'h807         Cannot be in Standard space (now in user custom read/write space)
UHARTID                 12'h014         12'hCC0         Cannot be in Standard space; should not be R/W (now in user custom read-only space)
PRIVLV                  12'hC10         12'hCC1         Cannot be in Standard space (also clashes) (now in user custom read-only space)

Signed-off-by: Arjan Bink Arjan.Bink@silabs.com