Generate RISC-V variant floating point testfloat vectors

Created by: jordancarlin

• Generate softfloat/testfloat variants for both RISC-V and IEEE flavors of floating point
• Update testbench_fp to select RISC-V or IEEE versions of the vectors automatically
• Switch regression-wally --testfloat and --nightly to run comprehensive tests on RISC-V variants and only a single IEEE variant
• Remove (almost) all IEEE-compliant floating point derived configs and replace them with standard RISC-V versions of these configs

NOTE: Currently many of the divider configurations (especially the ones with IDIV_ON_FPU) are not tested (they weren't tested before these changes either). They should either be removed or regression should be updated to test them, but that can be part of a separate PR.