Adds synthesizable RVVI FPGA hardware

Created by: rosethompson

Adds submodule verilog-ethernet to addins/verilog-ethernet to support a wide range of ethernet devices. Only the MII (100Mbit/s) device is modified to work with Wally. Adds the cvw/src/rvvi directory for synthesizable rvvi and packetized rvvi interface. Adds wrapper to cvw/testbench/common/rvvitbwrapper.sv for simulation of the rvvi interface. Adds top level parameter to testbench.sv to enable rvvi_synth. Adds top level parameter to fpgaTopArtyA7.sv to support hardware rvvi. Implements a software daemon to collect ethernet frames on a host computer and then reconstruct the rvvi interface to pass to ImperasDV.