Fully decode decompressed instructions, including hints and illegal registers/immediates

Created by: davidharrishmc

Fixes Lee's bug report of July 17, 2024. The decoder was not detecting that LDSP with rd=0 is illegal.

Our generator created another instruction which I am trying to determine why it causes an issue

The instruction in question is a C.LDSP 602e 011 0 00000 00111 10

From above rd=0 and uimm=111000, which I think is offset by 3, so effectively 111000|000 = 64+128+256 = 448

011 uimm[5] rd!=0 uimm[4:3|8:6] 10 C.LDSP (RV64/128; RES, rd=0)

Error (IDV) CSR register value mismatch (HartId:0, PC:0x0000000080000080 write_tohost+6): Error (IDV) Mismatch 0> CSR 342 (mcause) Error (IDV) . dut:0x0000000000000005 Interrupt:0 Code:5(Load access fault) Error (IDV) . ref:0x0000000000000002 Interrupt:0 Code:2(Illegal instruction) Error (IDV) Mismatch 1> CSR 343 (mtval) Error (IDV) . dut:0x00000000000001a5 Error (IDV) . ref:0x000000000000601e Error (IDV) testbench.idv_trace2api.state_compare @ 313440: MISMATCH

It appears the RTL reports a “load access fault”, whereas the REF reports “illegal instruction” From the spec it appears that if rd==0 (which it does), then this is a RES(erved) instruction, not a C.LDSP

Do you think Wally is decoding this as a C.LDSP rather than a reserved instruction, and that is why it gets the access fault ?