Add SoC config

Created by: infinitymdm

Changes in this PR apply only to the soc branch, not main or dev

This PR adds a new configuration file for the Wally RV64GC SoC using BSG's memory controller, as well as a number of changes relevant to our SoC tapeout effort.

Summary of changes:

• Bring the soc branch (relatively) up-to-date with main
• Integrate debug spec from #823
• Clean up previous SoC-related changes:
  • Delete testbench/testbench-soc.sv and merge its contents into `testbench/testbench.sv
  • Delete soc-specific dofiles
  • Use a few new config parameters to selectively enable PLL and BSG DMC support
  • Add a new config file config/soc/config.vh
• Get BSG's memory controller talking to Wally over AHB
  • Rewrite ahbxuiconverter.sv with FSM-based control and waaay simpler datapath
  • Add memory-mapped registers for configuring the memory controller
  • Add memory-mapped registers for configuring TCI 28nm PLL IP
  • Add "First stage bootloader" assembly procedures (under soc/fsbl) that set up the aforementioned configuration registers with valid test parameters
• Test Wally in SoC configuration
  • Configure testbench to use the Micron LPDDR model provided by BSG
  • Add self-checking procedure to tests/custom/lpddrtest
  • You can run tests against the SoC config using regression-wally --soc