Verilator Performance Improvement on Testbench

Created by: Karl-Han

As mentioned in #650 (closed) , the problems are tackled in the following ways:

• $finish is required for Verilator while causing problem in QuestaSIM
  • use macro to conditional compile the $finish and $stop for different simulator
• profiling error with 460% surplus
  • it turns out that it is very likely that it is related to the above problem as you can try to add the condition compile to resolve it
  • I checked out on https://github.com/openhwgroup/cvw/tree/d1a1345e4d88b1afa16754ecd1554d71aadfe796 and made modifications with the conditional compile macro on line 360, and it works as expected with 2% surplus
• Testbench is running much slower in verilator
  • My intuition for the modification is that I am trying to eliminate unnecessary operations, and I found that the loading and validating the test is included inside a always block.
  • as it turns out, this solution eliminates the problem and it runs faster on verilator than QuestaSIM
• Coding style is changed as #delays are removed https://github.com/verilator/verilator/issues/4858
  • Collaboratively work with David and remove all the #delay in code except the testbench
  • and it passes the regression.