Fixes some but not all of the Issue #405 bugs. Fixes non-cached atomics, zifence when there is no dcache, and more serious bug with compressedF not supressed on the last cycle of a bus fetch. (!576) · Merge requests · OpenHW Group / backup-20241120 / cvw

Created by: rosethompson

Fixed the zifencei bug (part of issue 405).
Fixed part of issue #405 (closed). The non-cache version of the bus controller did not have the correct supression of BusCommitted for a read only controller.
Hmm. Verilator is complaining about the parameter width. I'm not sure why so I changed to 1 bit.
Added logic for the non-cache atomics.
Atomics work correctly without a d cache.

Fixes some but not all of the Issue #405 bugs. Fixes non-cached atomics, zifence when there is no dcache, and more serious bug with compressedF not supressed on the last cycle of a bus fetch.