Added Zicond support
Created by: davidharrishmc
czero.eqz and czero.nez supported Pass riscv-arch-test tests Involves an extra mux on the B input of the ALU AND gate to choose A or 0 based on B.
Created by: davidharrishmc
czero.eqz and czero.nez supported Pass riscv-arch-test tests Involves an extra mux on the B input of the ALU AND gate to choose A or 0 based on B.
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