Got Verilator compiling! and Questa still simulates

Created by: rosethompson

• Progress.
• More progress. Most tests are passing in modelsim.
• Fixed some regression tests with David's help.
• Fixed bugs in the cbom test.
• Fixed bugs in the wally64periph signature.
• Fixed the last uninitialized memory issue in the priv tests.
• DON'T keep this commit.
• Almost working with modelsim and verilator.
• "Resolved" ram preload issues by replacing the RAM's types with bit from logic. Tested fpga synthesis.
• Ok that is a stange bug. The testbench used logic for the shadow ram, but the memory used bit. This caused questa to allocate huge amounts of memory and crash. Changing shadow ram to bit fixed the issue.
• Revert RAM logic to bit change. Added logic to hptw to prevent x propagation.
• Reverted logic to bit change.
• Updated tests with ending label.
• All regression tests which matter are running!