Properly gate LRUWriteEn with ~FlushStage

Created by: magpyed

LRUWriteEn is supposed to be gated by ~FlushStage. SystemVerilog's order of operations puts & above |, so the previous version had ~FlushStage and-ed with a single term of the LRUWriteEn expression. Added parentheses to fix this.

For some difficult-to-divine reason, this also fixes the overlogging for the cache simulator - fixing all non cbo-related discrepancies between Wally's cache and the simulator cache.