Adds Zicbom support for D-cache only. I-cache not yet supported. Tests 32 and 64 bit versions. Please rebuild regressions wally32 and wally64. To save rebuild time edit lines 11-12 of tests/riscof/Makefile (!383) · Merge requests · OpenHW Group / backup-20241120 / cvw

Created by: rosethompson

Cache cleanup.
Pushed performance of arty a7 to 23Mhz.
Clean up vcu118 synth scripts.
Fixed constraint in VCU118.
Added new signals to the vcu118 debug4 ila to help figure out why the new linux build's hptw fails.
Updateds to vcu118 constraints and device tree.
Initial CMO implementation. Just adds control signals into the L1 caches.
The L1 D cache now supports cache line (block) invalidation and partial support for clean and flush.
More progress towards cmo.
Added clean and flush to cache fsm.
CMOZ now implemented in the D cache.
Found first bug in CMO implementation.
Updated the hazard logic for CMO operations.
Fixed cbo instruction decode.
Might have working cbo clean and flush instructions.
Added cbom test to custom. Needs to be moved to wally-riscv-arch-tests.
Now we have invalidate, clean, and flush working.
Fixed issue when with flush miss.
Made a bunch of progress towards getting cbo instructions tested.
Working CBO tests for 64 bit!
Have a working 32 bit cbom test!
Modified rv32gc and rv64gc configs to enabled Zicbom.

Adds Zicbom support for D-cache only. I-cache not yet supported. Tests 32 and 64 bit versions. Please rebuild regressions wally32 and wally64. To save rebuild time edit lines 11-12 of tests/riscof/Makefile