Imperas found bug with hptw

Created by: rosethompson

• Updated global history branch predictcor with the gshare improvements.
• optimized branch predictor by removing unnecessary registers.
• Imperas found a real bug in virtual memory. If the instruction address spilled across two pages and the second page misses the TLB, the HPTW received a tlb miss at the address of the first page rather than the second. After the walk the TLB was updated with the PTE from the first page at the address of the second page.