Fixed issue #368 lint, but not simulation (!369) · Merge requests · OpenHW Group / backup-20241120 / cvw

Created by: rosethompson

Improved timing constraints for arty a7 to push clock speed to 20Mhz.
Updated arty a7 device clock speed for 20Mhz.
Removed all old references to the old flash card controller. Added git submodule for the flash card in addins. Replicated flash card top level for our changes into the fpga/src directory.
Removed old sdc from all configs.
Updated Arty A7 fpga config and device tree to 256MiB main memory.
Fixed lint errors for issue #368 (closed). Does not fix simulation errors. We made a design decision a long time ago to not support DTIM on the rv32gc config because LLEN was greater than XLEN.

Fixed issue #368 lint, but not simulation