Progress toward DC synthesis

Created by: davidharrishmc

Fixed some of synth.tcl to use parameterized design. However, synth is still failing with

make synth DESIGN=wallypipelinedcore TECH=sky90 CONFIG=rv32e FREQ=1000

... elaborate $my_toplevel -lib WORK Loading db file '/cad/synopsys/SYN/libraries/syn/gtech.db' Loading db file '/cad/synopsys/SYN/libraries/syn/standard.sldb' Loading link library 'scc9gena_tt_1.2v_25C' Loading link library 'gtech' Running PRESTO HDLC Error: Module or interface 'wallypipelinedcore' was not elaborated because no default or override values were provided for parameter(s) 'P'. (ELAB-2041) *** Presto compilation terminated with 1 errors. ***