First pass at testbench restructuring

Created by: rosethompson

• Changes required to make verilator compile wally's testbench to c++. Not actually tested in simulation yet.
• Removed comments around commented code for verilator.
• This parameterizes the testbench but does not use the verilator updates or the new testbench.
• Created temporary wrapper for lint.
• Progress towards new testbench.
• The new testbench is almost working except the shadow copy is not working.
• The testbench now at least runs the arch64i in rv64gc config. Still has several issues 1. need to remove all dead code 2. seems to still be double reading memory files sometimes. 3. batch mode does not work.
• Fixed the multliple reads of the same preload memory file.
• More cleanup.
• Compacted memory resets.
• Cleaned up testbench more.
• Now have most of the regression tests running again.
• Fixed another issue with the timing of memory resets in the new testbench.
• Updates to wave file.
• Resolved the duplicated check signature issue.
• Continued improvements to testbench.
• more testbench improvements.
• Found and fixed the source of the new testbench slow down. I accidentally increased the size of the signature buffer by 10x.
• Improved simulation speed by gating bitmanip zbc's clmul's X and Y inputs with BSelect != 11. Reduced simulation time from 3m45s to 2m35s.
• Removed old configs from function name module.
• Significant refactoring of testbench.
• Found a whole bunch of files still using the old `define configurations.
• Got the srams parameterized correctly now.
• Actually removed old `define configuration file for rv64gc. There were a lot of dangling problems.
• Deleted remaining old configs except fpga as I still need to create the parameterized version.
• Major cleanup of testbench.
• Added comment to uart LCR to check reset value after updating FPGA.
• Have the linux testbench working in the mean time. Before the consolidation.