CacheSim: Logger improvements, performance logging, sim wrapper

Created by: magpyed

Improvements to the logger: Only cacheable memory accesses are logged, and the enable signals have been tuned to exclude flushed instructions. Cache flushes and invalidations are logged separately (not via enable) now.

New CacheSim flags: -p/--perf to report the hit/miss ratio, and -d/--dist to report the distribution of operations. I also cleaned this file up a bit.

Simulation wrapper: in the sim directory, added rv64gc_CacheSim.py. This script runs each rv64gc test suite and runs the simulator on the I$ and D$ logs. This wrapper also takes the -p and -d flags. Make sure you enable logging in testbench.sv! If a different name for this wrapper is preferred, let me know.

Minor cache.sv change: We were previously passing in (LRUWriteEn & ~FlushStage) to cacheLRU's LRUWriteEn signal. However, inside cacheLRU, every time LRUWriteEn is used, it is with "& ~FlushStage." I took the route of passing in just LRUWriteEn to cacheLRU, since I feel that having cache.LRUWriteEn != cache.cacheLRU.LRUWriteEn will confuse future contributors.