Full I$ coverage

Created by: AlecVercruysse

This PR should bring the i$ coverage up to 100%.

Big changes include

• a big refactor of the cachefsm.
• Excluding from coverage the potential case where FlushStage (FlushD) asserts simultaneously as a write (SetValidWay) for the read-only cache. My reasoning is in the commit message (3fc6bb0c), but in short, I think it's impossible to hit.
• Changing some adress Muxes from mux3 to mux2 for read-only caches.
• Fixing last LRUUpdate coverage issues, and changing some genvar names to improve readability. Note that the textbook's description of LRU has some outdated signal names as well.

Note that the rv64gc_wally64priv test failed for me, but it failed for me on 2f6ed64 (the current upstream/main) as well. Please let me know if this is something unique to me!