Solves issue 172

Created by: rosethompson

• Minor change with the IFU in the decompress module, in the compressed instruction truth table. The truth table is already fully covered, removed redundant last case checking
• Formating white space
• Similifed the no byte write enabled version of the sram model.
• Added note about strange vivado behavior not inferring block ram.
• Fixed syntax error.
• Added Jacob's ILA script.
• Removed redundant stall signal to get spill coverage
• Simplified integer division preprocessing in fdivsqrt
• Division cleanup
• vm64 tests
• Fixed enabling machine timer interrupt
• Fixed WALLY-init-lib to return correctly even from traps from compressed instructions
• Bug fix: MTIME & MTIMEH registers are unimplemented and should fault when accessed
• Fixed priv.S to initialize stimecmp and agree with ImperasDV
• Fixed csrwrites.S to agree with ImperasDV. Now coverage tests pass iter-elf
• Added vm64check tests to cover IMMU vm64
• Commented WFI non-flush in writeback stage of hazard unit
• Improved RAS predictor coverage by eliminating unreachable StallM term
• Waived coverage on BTB memory with byte write enables tied high
• Added test coverage for floating point registers, some PMP addresses, as well as MTVAL and MCAUSE CSRs.
• Updated wally top level figure to fix issue 172.
• Updated wally figure again to increase resolution.