i$ coverage improvements

Created by: AlecVercruysse

A lot of I$ coverage issues are due to the fact that the read-only cache and rw-caches are described with the same verilog code. There were many opportunities to make the cache dirty/flush/write logic somehow dependent on READ_ONLY_CACHE to improve coverage.

Another significant change is adding ram1p1rwe, which does not have byte-enables. This is useful for the data memory of read-only cache, as well as the tag array for any caches, both of which always have every byte-enable high. One thing to note, however, is that coverage is disabled for the chip-enable during a write of this new memory.

I've written my reasoning for each change in the commit message for the change (and attempted to separate commits as much as possible). One extra thing to note are that for commit 3867142, the cachetagmem was also changed to ram1p1rwe for the D, not just the I. This makes sense since the byte-enable is not needed for tag memory. Turning off coverage for the chip-enable in ram1p1rwe, however, might adversely exclude coverage for the D$ cachetagmem, since it might be possible that a write could when the chip-enable is pulled low for D. I would appreciate suggestions for another way to deal with the chip-enable coverage for i memories if this is unacceptable.

Thanks!