Fixes multiple cache bugs and CacheSim.py bugs

Created by: rosethompson

Resolves issue #909 (closed). Please merge after PR #1088 is merged.

To summarize there were two main bugs in the cache.

1. A store hit sets the dirt bit. If the following instruction reads the same cache set, this dirty bit was not read as dirty but rather as cleared because of a structural hazard. The original cache design assumed the pipeline would insert a pipeline stall to avoid the hazard. The solution was a simple forward of the write data to the read data when writing the dirty bit. This hazard would cause an issue when the second instruction would need to cause a writeback. The cbo.clean and cbo.flush instructions revealed the bug.
2. The LRU was not correctly updated when the cache was stalled. The wrong set address was sent the LRU.

The cache simulator did not support cbo instructions and now does.