Optimized SPI Logic

Created by: JacobPease

I removed unnecessary logic, faulty logic, and changed signal names. All of this was tested on the FPGA and it also passes regression.

• Removed unused signals and renamed other signals. Removed a bunch of delay counters and simply reuse one counter for all delay types. Tested on FPGA and it also passes regression.
• More SPI optimizations.
• Removed impossible condition in receive register logic.