Fix DivSqrt lanes synchronization
Created by: lucabertaccini
This PR fixes the synchronization scheme for DivSqrt
lanes. In the case of CVFPU instances supporting SIMD
operations, such a scheme made the lanes wait for the others to complete their calculations even when the operation was scalar (i.e. EnableVectors = 1'b1
and vectorial_op_i = 1'b0
), thus never completing the scalar computation.
With this PR, the synchronization scheme is modified, deciding whether to synchronize with other lanes based on whether the current operation is vectorial (this guarantees correct execution also in the case of interleaved scalar/SIMD DivSqrt executions).
This PR targets another minor modification: some additional unused signals in specific configurations of fpnew_opgroup_multifmt_slice are tied to '0.