🔧 Add external reg enable to slices

Created by: michael-platzer

Hi,

this PR is a proposal to add an external register enable, overriding the local register enables generated from the internal valid and ready handshake signals, to the slice modules (fpnew_opgroup_[multi]fmt_slice) and the underlying opgroup modules.

The motivation for an external register enable is a better separation between control flow and data flow. Concretely, an external register enable would allow for the following:

• When a CVFPU slice module is instantiated as part of an ALU pipeline that also hosts another unit, such as an integer ALU, the external register enable can be used to avoid splitting the pipeline into an integer and a floating-point part and then merging them back together, but instead allows to control the individual pipeline stages of the CVFPU opgroups as well as the integer pipeline stages with a single main pipeline. This also solves the problem of re-ordering the output of individual pipeline branches in case the pipeline requires all operations to remain in order.
• An external register enable allows to run the control logic ahead of the dataflow, with the register enable signals passing through one or several FF buffers, which may help timing closure by separating the often critical ready signal path from the register enables of the FFs in the dataflow path.

The changes are intended to be as minimal as possible, with an additional reg_ena_i port added to the slice modules and each opgroup module, which supplies the external register enable signals. This input port can be tied to '0 if the external register enable shall not be used. Otherwise, the external register enable signals can be provided via this port and the in_valid_i be tied to '0 to disable the local register enables generated by the internal handshake signals.

The width of this reg_ena_i port corresponds to the number of pipeline stages - however, an additional parameter ExtRegEnaWidth is required to catch the case where the number of stages is 0. Finally, the slice modules also gained a parameter ExtRegEna which must be set to 1'b1 to avoid Nan-boxing all outputs in the absence of internal valid signals.

Note that the external register enables are only available when directly instantiating the fpnew_opgroup_[multi]fmt_slice modules or an individual opgroup module. The fpnew_opgroup_block disables the external register enables by tying reg_ena_i to '0 and leaving the ExtRegEna at its default value of 1'b0. We have used the formality tool to verify that instantiating fpnew_top with these changes is still formally equivalent (using Synopsys formality) to the same instantiation without these changes.