Fix and extend `fpnew` SIMD support (Ara Vector processor branch)

Created by: mp-17

Hello everyone,

This PR follows the discussions we had around reducing the entropy that exists among our projects. We have many different versions of cva6 and fpnew around, and we are trying to converge.

As discussed here https://github.com/openhwgroup/cva6/pull/1102, this PR aims to merge into the main branch (develop?) the fixes and light modifications introduced to better support the RISC-V V extension. Thus far, these modifications were only used in the Ara system (https://github.com/pulp-platform/ara).

The modifications include the following:

1. Fix bug triggered by vectorial divisions/sqrts.
2. Add support for RISC-V-compliant classify when the width of the vector elements is at least 10 bits.
3. Add a mask input signal to mask the exceptions from inactive SIMD elements.
4. Add support for rounding toward odd.

Feel free to let me know if you need additional details!