:adhesive_bandage: Fix illegal Verilog `'0`

Created by: zarubaf

Verilog does not allow '0. I've revendored the sources with the proper length of the 0 literal.

Unfortunately I've had some whitespace fixes that apply when re-vendoring. Not sure what the main problem is but best to ignore them in the UI by disabling the whitespace changes.

/cc @michael-platzer