:adhesive_bandage: Fix divsqrt when using external reg enable

Created by: michael-platzer

As a follow-up to #89, this PR adds some miscellaneous logic required to use the divsqrt slice with external register enable signals. The divsqrt requires multiple cycles to compute a result, which was not taken into account in #89. With the new changes, a pipeline driving CVFPU slices with external register enables can conservatively wait for the maximum number of cycles expected to complete a divsqrt operation before pushing the next operands into the slice.

As with #89, when reg_ena_i is tied to '0 and the ExtRegEna parameter is 1'b0, then the changes in this PR have no effect and the logic remains the same. The newly added ext_op_start_q flip-flop always holds 1'b0 if reg_ena_i is tied to '0, which most synthesis tools should recognize and thus optimize it away.