Flist: Split Flists for SV32 and SV39 to prevent Questasim elaboration errors

Created by: niwis

Fixes the questasim simulation flow. In particular: 1. Port width mismatch in ariane_testharness. Therefore, propagate the AXI_USER_WIDTH from ariane_testharness to ariane_peripherals ➡ #1043 2. riscv-tests do not signal success or failure after execution in questasim. This is due to the rvfi_tracer intercepting ecalls and terminating the simulation prematurely (they are needed by the proxy kernel for communication). Therefore, disable RVFI_TRACE for regular simulations per default. ➡ #1141 3. Some benchmarks time out in Questasim simulation. For instance, rsort requires over 4M cycles on the WB cache, which is well above the current default timeout of 2M cycles (not sure if this is due to a performance regression). Therefore, set the default timeout to 6M cycles which is a safe value for all riscv tests and benchmarks. 🗑 4. Fix the compilation order for Questasim (#1008 (closed)). ➡ #1043 5. Increase the testbench's memory size (#1014 (closed)). 🗑 6. Questasim will error when elaborating the SV32 MMU for 64-bit CVA6. We had this issue a while again and filtered out the incompatible MMU version depending on the target. This was broken again with the change to file lists. Hence, split the MMU out of the common file list into a separate one that can be chosen from the Makefile. I believe using bender would be a more elegant and maintainable solution at this point. Furthermore, why the file name inversion (Flist.<target>)?