cache_subsystem: Parametrise AXI interface

Created by: niwis

Parametrise the AXI interface of CVA6. With this PR, both cache subsystems support variable AXI address widths. The write-through cache furthermore supports variable AXI data widths. Moreover, this PR includes a modular AXI testbench for the WT cache to test the introduced changes. The following configurations of the WT cache have been verified:

XLEN   Cacheline Width   AXI data width   AXI address width
64     128               64               64
64     128               128              52
64     512               128              64
32     512               256              48
32     64                32               48

This PR is based on an earlier version on the pulp-platform fork (https://github.com/pulp-platform/cva6/pull/1). The review there was implemented in this version.