[tracing] Uniformize VCS and Verilator support of waveform dumps.

Created by: zchamski

This PR adds the CVA6-side support for VCD and FST dump generation using Verilator. It has a companion PR on core-v-verif (branch cva6/dev) that provides the unified trace control for VCS and Verilator in the verification flow.

• Makefile (verilate_command): Set defines according to requested trace mode (fast/compact). Request inclusion of appropriate support files (source code, compression libraries) into Verilator Makefile.
• corev_apu/tb/ariane_tb.cpp (toplevel): Include appropriate trace header according to tracing mode (FST or VCD). (usage): Add description of flag and sample command line for FST tracing. (main): Add long and short FST format option. Add FST format handling.
• corev_apu/tb/ariane_testharness.sv: Add explicit request for named trace file according to selected tracing mode. Enable full trace in Verilator in-RTL config.

Signed-off-by: Zbigniew Chamski zbigniew.chamski@thalesgroup.com