Update to synthesis and simulation gate flow

Created by: Gchauvon

core/Flist.cv32a60x: [NEW] Add Flist for gate simulation with cv32a60x configuration core/Flist.cv64a6_imafdc_sv39: Update to support uvm testbench match $DESIGN_NAME variable in Makefile pd/synth/Makefile: Add $TARGET variable to chose which config to synthetise Change DESIGN_NAME to cva6 module so it is the top module pd/synth/cva6_synth.tcl: Update to match new topmodule pd/synth/dc_setup.tcl;dc_setup_filenames.tcl: Uptade to match new path with $TARGET pd/synth/tc_sram_wrapper_...sv: Add a copy of tc_sram with specific parameters to replace tc_sram in netlist @JeanRochCoulon @yanicasa can you look at that ?