rvfi_tracer.sv: Fix log format of FP regs written by compressed insns.

Created by: zchamski

Purpose

This PR modifies the generation of logs from RTL testbench.
Previously, the names of FP registers written by compressed instructions were incorrectly printed as integer register names. This change extends the FP-specific printing format to destination regs of both uncompressed and compressed instructions that set an FP register.

Details

The only compressed instructions that set a floating-point destination register are FP loads from memory. In the RISC-V ISA spec (both v2.2 and 20191213) FP loads exist in word and doubleword versions (C.FLW*, C.FLD*), each with register-indexed and SP-relative addressing (C.FLW/C.FLWSP and C.FLD/C.FLDSP, respectively).

The spec allows FP regs to be 64 bits wide on an XLEN==32 architecture with the D extension. Therefore, doubleword FP loads C.FLD/C.FLDSP are valid for both RV32 and RV64 if the D extension is enabled. They will be recognized by the tracer for both XLEN==32 and XLEN==64, even though with the current settings in core/include/ariane_pkg.sv only CV64A6 can have double-precision FP support.

Single-word compressed loads C.FLW/C.FLWSP are specified as RV32-only (https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf, pages 101 and 103, and Table 16.5/16.7). They will only be recognized when XLEN==32.

The encoding of the instructions uses the same func3 values for both register-indexed and SP-relative addressing modes. The distinction between the addressing modes is made through the compressed instruction quadrant used (bits [1:0] of the compressed instruction encoding), with register-indexed instructions placed in quadrant 0 and the SP-relative ones placed in quadrant 2.

Testing

The matching test set has been submitted as PR https://github.com/openhwgroup/core-v-verif/pull/1392.

Files changed

• corev_apu/tb/rvfi_tracer.sv: Recognize compressed insns that set FP regs so that all FP register commits are correctly formatted.

Signed-off-by: Zbigniew Chamski zbigniew.chamski@thalesgroup.com