Adding Support for Zba, Zbb, Zbc and Zbs extensions to CVA6

Created by: M-Ijaz-10x

Introduction

This PR is the continuation of issue-451 and adds support for zba, zbb, zbc and zbs extensions under the wrapper of a compiler directive BITMANIP. These changes have been tested with self-written single instruction tests and using the compliance tests with the core-v-verif infrastructure.

Implementation

Added the support for all the ratified bitmanip extensions as defined under this bitmanip-spec

• Zba extension (Address generation instructions)
• Zbb extension (Basic bit-manipulation instructions)
• Zbc extension (Carry-less multiplication instructions)
• Zbs extension (Single-bit instructions)

Integration of bitmanip hardware with cva6

The major changes have been done in the decoder which includes adding the RISC-V Bitmanip opcodes, selecting the Functional Unit from Multiplier and ALU of the Ariane core and implementing design logic for Bitmanip instructions in ALU and Multiplier FUs.

Verification

Assembly Tests

The functionality of each implemented Bitmanip instruction has been verified by running individual assembly tests related to that particular instruction on the updated design.

Core-v-verif environment

The OpenHW group’s core-v-verif verification environment has been modified to support the latest riscv-arch-test infrastructure (PR: Added the support to run latest riscv-arch-tests in core-v-verif CVA6 infrastructure) and used to run the compliance tests (base tests + bitmanip tests) on the updated design. All the required bitmanip tests have successfully passed.