Add CoreV-X-Interface, top hierarchy modification and rs3 for global purpose register file.
Created by: Gchauvon
Hello,
I propose a first implementation of the CoreV-X-Interface protocol for the cva6. You'll find the protocol here: CoreV-X-Interface.
My implementation supports all mandatory interfaces from the protocol:
- Issue interface
- Commit interface
- Result interface
Memory Interface and memory result interface used to connect coprocessor to CPU memory are not supported yet. Compressed Interface may not be necessary as cva6 already support Compressed extension.
CoreV-X-Interface Implementation
CoreV-X-IF is enabled via the CVXIF_PRESENT flag in ariane_pkg.sv.
All illegal instructions are decoded under the R4-format. A new functional unit called cvxif_fu.sv is implemented in the ex_stage.sv and will proceed to create request on the X-Interface to offload illegal instructions. This module handle responses from the coprocessor aswell.
In case an instruction is rejected ( illegal for CVA6 and coprocessor ), an ILLEGAL_INSTR exception is sent via the writeback bus. If the instruction is accepted, the coprocessor will give the result of the instruction so it can be writeback to the register file via the writeback bus aswell.
Hierarchy modification
This PR contains a modification of the hierarchy for top modules.
A new module called cva6.sv is basically ariane.sv with cvxif ports.
ariane.sv is now a wrapper containing cva6.sv and an example coprocessor when CVXIF is enable. ariane.sv keeps the same inputs/outputs as before so people that already have instantiated ariane can still use the repository.
Testharness now looks like this:
3rd read ports for ariane_regfile
I also added the possibility to have a 3rd read port for the global purpose register ( ariane_regfile ). The CoreV-X-Interface protocol allows the CPU to transmit 3 sources registers to the coprocessor and it was my use case during development. I made it configurable via the ariane_pkg::NR_RGPR_PORTS because adding this 3rd port has an impact in area.