wb_dcache: Forward "atomic transactions" to AXI

Created by: colluca

Description

This PR removes handling of atomic operations inside the WB cache. It forwards them instead on the AXI bypass interface, to be handled closer to memory.

Swap, fetch-and-op and op type atomics are presented on the interface as AXI5 "Atomic Transactions". Load-reserved and store-conditional are presented on the interface as AXI4 "Exclusive accesses". This is aligned to how atomics are expected in the riscv_axi_atomics module.

Status

• Forward swap, fetch-and-op and op type atomics to AXI interface Miss-hander FSM updated. AXI adapter extended to present AXI5 "Atomic transactions" requests and handle respective responses.

• Adapt testbench A riscv_axi_atomics module is instantiated and connected between the DUT and the TB memory to handle atomics. The ensemble of the two modules should equal the previous DUT in terms of functionality, hence the rest of the TB can remain unaltered.

• Pass tests with swap, fetch-and-op and op type atomics

• Forward load-reserved and store-conditional to AXI interface Extend AXI adapter to present AXI4 "Exclusive access" requests and handle respective responses.

• Pass tests with load-reserved and store-conditional atomics