Mask non-enabled interrupts in WFI control

Created by: colluca

This PR addresses issue #321 (closed).

The current revision of the RISC-V Priviliged ISA specification states:

The operation of WFI must be unaffected by the global interrupt bits in mstatus (MIE and SIE) [...], but should honor the individual interrupt enables (e.g, MTIE) (i.e., implementations should avoid resuming the hart if the interrupt is pending but not individually enabled).

This behaviour is not mandatory but it is suggested (could we say also intuitive?). Furthermore it would have positive implications on power.

Suppose the core is stalled on a WFI. Suppose timer interrupts are disabled, as we are expecting a SW interrupt to resume the hart. By specification, a timer interrupt will eventually become pending, and if this condition occurs before the SW interrupt arrives, the hart will resume from the WFI and start looping until the SW interrupt pending bit is set or the timer interrupt bit is cleared. In both cases this results in the core doing more work than with the implementation suggested by the spec.