PMP integration

Created by: Moschn

This PR adds PMP support to Ariane/cv6. A few comments on the implementation:

• Adds a new PMP access check unit
• The unit is instantiated in three places in the pipeline:
  • two in the MMU (one for instruction fetch and one for data access)
  • one in the PTW that checks pt accesses
• Because Ariane does not support unaligned data accesses, we have decided to only implement granularity 3 (2^3 = 8 bytes aligned).
• The number of PMP entries is configurable in ariane_cfg_t. The default is set to 8 for now (I am open to set it to 0 to not cause any breakage for users). If the number is set to 0, all of the PMP units are disabled and there should not be any hardware overhead.

This has been tested with:

• the PMP test in riscv-tests. However, the PMP test in riscv-tests works with granularity 2 (4 byte access). So in order to check the ariane implementation one has to change the test and change the granularity to 3 (or 8).
• a custom version of the keystone enclave framework
• OpenSBI boots the new core. However the configuration of OpenSBI would have to be modified to indicate that Ariane does support PMP. Without this modification, it does not work.
• Linux obviously still boots because it does not interact with the PMP entries (verified on the FPGA).