address length: make configurable physical and virtual address length

Created by: JeanRochCoulon

Why to request a pull for this modification? In RISCV specification, two types of address are defined: physical and virtual address. Physical address is max 56 bits and virtual address is 39bit (sv39) or 48bits (sv48). In Ariane implementation, physical and virtual addresses are implemented on 56 and 64bits. Address length has impact on a lot of functionalities, scoreboard or caches for instance. By implementing two RTL variables, PLEN (as physical length) and VLEN (as virtual length), address length becomes configurable. By setting PLEN=32 and VLEN=39, kgate reduction is about 40kgates. I think it would be nice to integrate such a modification in main line to stick to the RISCV specification and reduce the gate count.

Modification:

• Only Ariane has been modified, not testbench. No impact on Ariane IOs.
• 36 files have been modified.
• As STD_CACHE is deprecated, it has not been modified. Keep the original configuration (VLEN=64 and PLEN=56) when using STD_CACHE.

•  The following constraint must be met: PLEN > VLEN

• Regression suite is PASS when VLEN/PLEN=64/56 and 39/32.
• Test traces have been compare cycle by cycle. No discrepancy has been detected between before and after modification.
• No additional Verilator warnings due to this modification
• Synthesis shows a 10% of gate reduction.

++, Jean-Roch