Add preliminary support for Nexys Video board

Created by: xushengj

This PR adds basic support for Digilent Nexys Video Artix-7 FPGA. The FPGA device is XC7A200T and is supported by Vivado WebPACK version.

Notable performance and functionality issues comparing with Genesys II:

1. Vanilla ariane core has a critical path delay of about 24-26 ns along FPU datapath on XC7A200T, and adding latency to FPU moves the critical path to integer data path with delay of about 23 ns. Therefore in this PR the clock is set to 40MHz and floating point instructions have 1-2 more cycles of latency.
2. Nexys Video board has only 512MB DDR3 memory.
3. Although Nexys Video board has identical RGMII interface for Ethernet, ariane-ethernet module keeps having timing violations and the ethernet just don't work.
4. (Needs help) After linux initialize the console, the baud rate somehow drops from 115200 to something near 108000. I haven't figured out what goes wrong. Any help is appreciated.

Major changes include:

1. Reorganized fpga/src/bootrom. Platform dependent sources are moved to subdirectories and Makefile will use $BOARD to choose one during bootrom generation. To generate the bootrom for Nexys Video board, run make clean && make all BOARD=nexys_video in fpga/src/bootrom.
2. Changed tcl script for xlnx_clk_gen to support Nexys Video board. The memory interface can at most run at 400MHz and the mig cannot generate 200MHz ui_clock, so a 200MHZ reference clock must be generated there.
3. New constraint file and SystemVerilog header for Nexys Video board.
4. Minor changes in rest of repository to account for this board.