[Xcelium flow] Fix initialization of memory array for simulation
Created by: CoralieAllioux
This PR aims at fixing sram initialization in tc_sram memory model. Initialization of SRAM in tc_sram.sv model is exceeding tool limit at runtime. Simple fix is to use a for loop instead of assigning the whole signal.
It contributes to task https://github.com/openhwgroup/cva6/issues/1829