[riscv-config] Align CV32A65X spec on adoc, cleanup defs. Fix CSR updater.

Created by: zchamski

Major update of the riscv-config spec of CV32A65:

• ISA string contains Zcb at the correct position
• MISA:
  • contains the 'B' bit inferred from simultaneous presence of Zba, Zbb and Zbs
  • the EXTENSIONS field is read-only
• 'read-only zero' registers have type 'ro_constant: 0x0'
• CSR fields which are 'read-only 0' are marked as 'implemented: false'
• PMPADDRn for n > 15 are declared 'accessible: false' on RV32
• PMPCFGn for n > 3 are declared 'accessible: false' on RV32
• PMPADDR8..PMPADDR15 have type 'ro_constant: 0x0'
• MTVAL has type 'ro_constant: 0x0'

The CSR updater YAML was adjusted to:

• leave MISA reset value unchanged
• keep 16 PMPADDRn registers and 4 PMPCFGn registers (until the CSR updater Python code is changed to discard registers marked 'accessible: false'.)