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Update VCS compile flow to 2-step flow in testharness and update UART to version 0.2.1

Eclipse Webmaster requested to merge github/fork/xiaoweish/support_sverilog_uart into master

Created by: xiaoweish

  1. Update UART to version 0.2.1
  2. Replace VHDL UART as SystemVerilog UART, and then
  3. Simplify VCS compile flow from 3-step flow to 2-step flow.

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