[UVM] Few LRM compliance fixes

Created by: CoralieAllioux

Those fixes are suggested in the context of supporting Cadence Xcelium simulator for cva6 verification.

The usage of keyword inside should be used as followed: variable inside {values or range}. The {} brackets are mandatory. See https://www.chipverify.com/systemverilog/systemverilog-constraint-inside

Concerning packages, the keyword endpackage should not be followed by ;.

This has been check with VCS 2021.09.