Maturity fixes and AXI extensions for write-through cache system.

Created by: msfschaffner

This PR contains a few bugfixes in the write-through cache system, as well as several maturity fixes.

Further, I restructured the AXI memory plumbing of the write-through cache system such that we have a separate AXI adapter now (instead of an L15 adapter, chained with an AXI adapter). This adapter also supports atomic ops and LR/SC transactions (but this still needs to be tested together with the exclusive adapter).