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Generate separate per-target logs when simulating.

Eclipse Webmaster requested to merge github/fork/ThalesSiliconSecurity/feature/per-target-logs into master

Created by: zchamski

  • verif/sim/Makefile (veri-testharness): Don't add target name to waveform file name.
    (vcs-uvm): Ditto.
  • verif/sim/cva6.py (run_assembly): Add target name to log file name.
    (run_elf): Ditto.
    (run_c): Ditto.
    (iss_sim): Ditto.
    (iss_cmp): Ditto.

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