Break Timing Loop in Axi Adapter Arbiter of WB Cache

Created by: domenicw

There exists a timing loop in the WB cache caused by the axi_adapter_arbiter module. This PR fixes it by breaking the connection between the rsp_i.gnt and rsp_o[sel_q].gnt signals. At the same time, this PR also removes an unnecessary cycle delay between two requests on the same port.