Fix bytewidth parameter in OpenPiton bootrom AXI-lite bridge

Created by: dpetrisko

The current bootrom in riscv_peripherals.sv has an AXI-lite bridge that assumes 64b alignment, regardless of the request size. This is incompatible with requests of 32b i.e. I$ fetches which do not fill the full bus width. The erroneous behavior is that the 32b request will not be duplicated in the returning P-Mesh request, which violates the protocol.

This PR fixes this parameter to 0, which informs the bridge to consider the request size when packing the bus on request returns.