serdiv - Reduced worst-case latency

Created by: Seek64

Description

In the current version, the serdiv module takes between 1 and WIDTH+2 cycles from the incoming request (in_vld_i) until the assertion of the valid signal (out_vld_o). The worst case scenario is a division by 0 or -1, as the counter gets set to WIDTH (see line 108). By introducing fast paths for these two cases (similar to div_res_zero), the maximum latency can be reduced to WIDTH+1 and divisions by 0 or -1 only take a single cycle now. We verified the functionality of both the original and proposed design with a set of formal properties. We have not checked if these changes affect the critical path in any way.

Changes

• Added a new register op_b_neg_one_q which indicates if b is -1. The lzc_b_no_one signal is now used to determine if b is 0 or -1.
• Introduced a fast path for 0 and -1 by adjusting the FSM and out_mux accordingly.
• Reduced the counter width by 1, as its maximum value changed from WIDTH to WIDTH-1.